This invention relates to semiconductor devices including both a bipolar transistor and insulated-gate field-effect transistors.
Although majority-carrier devices are intrinsically very much faster than bipolar structures, this speed is acquired at the expense of power handling, particularly for high voltage devices. This disadvantage is associated with the very high parasitic series resistance of the non-conductivity-modulated drain drift region and is a fundamental limitation for a majority carrier device. By way of contrast, bipolar devices are able to trade speed against dissipation through use of life-time killing, base-collector clamping, emitter-shorting and other such techniques for controlling conductivity-modulation or for extracting injected charge. A compromise between the properties of bipolar and majority carrier devices can be achieved by using the two types of device in combination. Background prior art structures of this general type are shown in "IEEE Proceedings of the Power Electronic Specialist Conference", 1983, pp. 144-149, IEEE Pub. 0275-9306/83/0000-0144; U.S. Pat. No. 4,729,007; WO85/04285; EP-A-159663; and WO83/00407.
Semiconductor devices have been proposed which comprise a bipolar transistor having an emitter region of one conductivity type interfacing with a base region of the opposite conductivity type, the base region interfacing with a collector region of the one conductivity type, a first insulated gate field effect transistor providing a gateable connection to the emitter region of the bipolar transistor, and a second insulated gate field effect transistor for providing a charge extraction path from the base region when the bipolar transistor is turned off.
EP-A-180255 describes such a semiconductor device in which four insulated gate field effect transistors are integrated and merged with a bipolar transistor. As described in EP-A-180255, the body of the semiconductor device forms the collector regions of the bipolar transistor and islands of the opposite conductivity type are provided adjacent one surface of the semiconductor body forming, alternately, a base region of the bipolar transistor and a drain region of the first insulated gate field effect transistor so that each base region is surrounded by drain regions of the first field effect transistor. In the discussion below of EP-A-180255 a single base region having on either side a drain region of the first insulated gate field effect transistor will be considered in the interests of simplicity.
As described in EP-A-180255, the first insulated gate field effect transistor has an insulated gate overlying a channel area provided by the body region between the base region and a first one of the two drain regions, so providing a gateable connection to the base region to enable extraction of carriers from the base region when the bipolar transistor is turned off. The emitter region of the bipolar transistor is disposed in the base region remote from the insulated gate of the first insulated gate field effect transistor. A source region of the second insulated gate field effect transistor is disposed in the second drain region adjacent the emitter region and an insulated gate overlies a channel area provided by the second drain region and the base region to provide a gateable connection to the emitter region. The third insulated gate field effect transistor is a vertical device provided by the inclusion of a source region in the base region remote from the emitter region so that the area of the base region underlying the insulated gate of the first insulated gate field effect transistor provides the channel area and the collector or body region forms the drain region of the third insulated gate field effect transistor which acts to provide base drive to the bipolar transistor. The fourth insulated gate field effect transistor is another vertical device with the body region forming the drain region of the device and is disposed in parallel with the bipolar transistor, the source of the second field effect transistor forming the source of the fourth field effect transistor and an area of the drain region of the first field effect transistor underlying the insulated gate of the first field effect transistor forming the channel area of the fourth insulated gate field effect transistor.